(2020). SystemVerilog for Hardware Description RTL Design and Verification / by Vaibbhav Taraate. [electronic resource].
Citazione stile Chigago Style (17a edizione)SystemVerilog for Hardware Description RTL Design and Verification / by Vaibbhav Taraate. [electronic Resource]. 2020.
Citatione MLA (9a ed.)SystemVerilog for Hardware Description RTL Design and Verification / by Vaibbhav Taraate. [electronic Resource]. 2020.
Attenzione: Queste citazioni potrebbero non essere precise al 100%.